Key Takeaways: - Hybrid bonding is essential for the interconnect density that high-bandwidth workloads require.
- Successful implementation depends on control of surface chemistry and surface topography — clean surfaces with topography that can accommodate expansion during bonding.
- To improve interface quality and manage stresses related to thermal expansion mismatch, manufacturers are considering alternatives to the “standard” copper/silicon dioxide bonding surface, including alternative dielectrics, passivating metals, and compliant polymers.
Copper-to-copper bonding enables unprecedented interconnect density between devices, but it introduces extreme sensitivities to topography and contamination. Engineers are pursuing different combinations of dielectrics and metals to provide more planar, more stable bonded structures than exist today. The move to copper-to-copper bonding is driven by modern computing’s insatiable demand for data. Generative AI tools are trained on datasets that incorporate a substantial fraction of the entire public internet. Autonomous vehicles collect data from arrays of sensors and cameras both inside and outside the vehicle. Industrial processes monitor every variable that might be relevant. Analyzing such large volumes of data consumes enormous amounts of bandwidth. Sensor data moves from the point of collection to a central computer and often to a remote data center. Training data moves from storage media to memory elements to a central processor. Calculated results move back to the end user. From individual chips to data center architecture, bandwidth is a key constraint for modern circuit and systems design. At the level of individual chips, transistors continue to shrink while memory arrays continue to grow. Connecting the two requires increasingly dense interconnects. More density within a chip is part of the motivation for
3D-ICs, which build structures like RRAM arrays directly on top of CMOS logic. At the system level, 3D packages use solder bumps to attach chiplets to interposer structures. As interconnect pitch is reduced, though, solder bumps become less reliable. There simply isn’t enough material to make a robust connection. Copper-tin intermetallic compounds can increase resistance or lead to mechanical failures. Instead, manufacturers are turning to direct copper-copper bonding. The first manifestation of copper-copper bonding, thermocompression bonding (TCB), places copper studs on both of the surfaces being bonded. As the name implies, heat and pressure fuse the two copper surfaces together. As interconnect density continues to increase, though, the mechanical demands of TCB become untenable. High temperatures and pressures can cause interconnects to buckle and shift, leading to performance degradation and even outright failure. Copper studs increase the overall package thickness. Hybrid bonding, or direct copper-copper bonding, offers a
further density improvement. It places the two chips flush against each other, attaching copper-to-copper and dielectric-to-dielectric with no intervening material. It reduces overall package thickness and maximizes interconnect density. And it scales well from initial implementations at 10 µm pitch. Researchers at imec have demonstrated hybrid bonding with interconnect pitches as low as 400 nm.[1]
Making a clean bonding surface Hybrid bonding is conceptually simple. Place two clean, activated surfaces in contact with each other, and dangling bonds at the interface create a robust connection at low temperature. In practice, though, the challenge begins earlier with the creation of a “clean” but “active” surface. Under ambient conditions, pure metallic copper quickly forms a native oxide layer. Silicon dioxide, on the other hand, provides a stable, non-reactive surface, which is a key reason it is a dominant dielectric in the IC industry. Typical hybrid bonding processes use thermal or plasma activation of the SiO2 surface to create a hydrophilic -OH-terminated layer. If two such surfaces are in contact, they readily form O-Si-O bonds at the interface. Meanwhile, a citric acid rinse helps remove copper’s native oxide. Once the two surfaces are in contact, actual bonding depends on the rate of copper surface diffusion. In principle, according to Hiroaki Tatsumi and colleagues at Osaka University, nanotwinned copper with exposed (111) planes should allow more rapid diffusion and facilitate void closure and grain growth. In simulations, though, they found that twin boundaries stabilized the surface and prevented atomic rearrangement. Nanocrystalline structures with abundant grain boundaries saw significant surface rearrangement and successful void closure.[2] Two key goals of surface preparation optimization focus on reducing the bonding temperature and avoiding interfacial defects. Plasma cleaning followed by bonding under vacuum minimizes bonding temperature with near-ideal surfaces. This is a relatively expensive solution, though, as the cleaning, alignment, and bonding steps all need to take place without breaking vacuum. Alternatively, a review paper by Yueting Zheng and colleagues at Dalian Jiaotong University discussed the use of self-assembled monolayers to protect the copper surface during the preparation of SiO2.[3] Here, the challenge is to desorb the protective monolayer before bonding without either allowing oxidation or leaving residual contaminants behind. Instead, some groups have used a passivating metal layer. Silver and ruthenium, for example, are both less prone to oxidation and compatible with copper. As conductive metals, they can remain in place without degrading performance. Copper diffuses through the passivating metal, forming a permanent bond. Managing surface topography After the chemical characteristics of the two surfaces, the surface topography is the next important factor in successful hybrid bonding. Even at low bonding temperatures, copper expands more than the surrounding silicon dioxide. Thus, the ideal topography has slightly recessed copper pads in a planar SiO2 surface. Thermal expansion during bonding closes the gap between the two copper surfaces. Achieving the desired topography requires a well-controlled CMP process. If the amount of copper dishing is too small, the void between the surfaces will close while the copper is still expanding, creating potentially damaging stress. If there is excessive dishing, the gap between adjacent pads will not close completely. The simplest applications of hybrid bonding involve copper pads in an SiO2 matrix. However, the CTE mismatch between copper and SiO2 is relatively large. In large features, such as TSVs, the stress induced by copper expansion can cause cracking and delamination. Alternative dielectrics like SiCN may offer superior performance relative to SiO2. Work at imec found that SiCN gave higher bonding strength and better thermal stability.[4] Adding a compliant polymer or curable adhesive can also reduce bonding stress. Sukkyung Kang and colleagues, working with benzocyclobutene (BCB), learned that precision CMP of partially cured BCB is effectively impossible. Abrasive particles embed themselves in the soft polymer surface, where the polishing pad simply glides over them. Instead, Kang used an argon plasma treatment to harden the BCB surface and produce more conventional polishing behavior. Stress between the hardened top surface and the bulk material caused surface wrinkling, which facilitated slurry flow. Because BCB has a higher CTE than metallic copper, the desired topography features a slightly recessed BCB layer relative to copper.[5] 
Fig. 1: CMP behavior of partially cured BCB, with and without argon plasma treatment. Source: Ref. 5 More complex interfaces are possible, even likely. One of the goals of heterogeneous integration is to combine optical components, logic, and memory in a single package. The advantages of hybrid bonding — high interconnect density with minimal vertical thickness — are equally relevant to optical and RF devices based on materials other than silicon. So are the challenges of surface cleanliness and surface topography. References - B. Zhang et al., “Scaling Cu/SiCN Wafer-to-Wafer Hybrid Bonding down to 400 nm interconnect pitch,” 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 312-318, doi: 10.1109/ECTC51529.2024.00058.
- Hiroaki Tatsumi, C.R. Kao, Hiroshi Nishikawa, “Atomistic behavior of Cu–Cu solid-state bonding in polycrystalline Cu with high-density boundaries,” Materials & Design, Volume 250, 2025, 113576, ISSN 0264-1275, https://doi.org/10.1016/j.matdes.2024.113576.
- Yueting Zheng, Hao Cui, Anyang Yu, “Advances and challenges in Copper–Copper bonding for 3D packaging interconnects,” Journal of Science: Advanced Materials and Devices, Volume 11, Issue 2, 2026, 101155, ISSN 2468-2179, https://doi.org/10.1016/j.jsamd.2026.101155.
- S. -A. Chew et al., “The Challenges and Solutions of Cu/SiCN Wafer-to-Wafer Hybrid Bonding Scaling Down to 400nm Pitch,” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413829.
- Sukkyung Kang, et al., “Chemical Mechanical Polishing of Plasma-Modified Cu/Polymer Interfaces for Advanced Hybrid Bonding,” Adv. Sci. 2026, 13, e12611 DOI: 10.1002/advs.202512611
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